Verification testbench with coverage for a FIFO and UART block

Kaveri Silicon Labs is taping out its second sensor-hub chip in nine months. On the first chip, a pointer-wrap bug in a FIFO slipped through simulation, corrupted one byte in every 4,096 under heavy traffic, and forced a metal respin that cost about ₹1.2 crore and four months. The verification lead's rule for this chip is simple: no block is signed off without a written plan, a self-checking testbench, a coverage report that closes every item in the plan, and proof that the testbench catches injected bugs.

You will verify two small blocks from the chip: - a synchronous FIFO, 8 bits wide and 16 entries deep, with full, empty and almost-full flags (almost-full at 12 entries) and sticky overflow and underflow error flags; - a UART with 8N1 framing, a programmable baud divisor, 16-times oversampling on receive, and the FIFO on its transmit and receive paths.

The company's RTL is confidential, so you will first write a small FIFO yourself from the specification, then verify it as if someone else wrote it. For the UART, you will write a simple RTL model or use an open-source UART core with a permissive licence, and say which.

Everything runs on open tools: Icarus Verilog or Verilator as the simulator, cocotb for the Python testbench, cocotb-coverage for functional coverage, Verilator's coverage for code coverage, and GTKWave for waveforms. No FPGA board or licence is needed.

Done looks like a verification plan, a testbench with a reference model and scoreboard, constrained-random tests with a seed you can replay, a coverage report at 100% of planned functional bins and at least 95% line coverage, a bug-hunt table showing the testbench catches at least 5 of 6 injected bugs, and a short sign-off report the verification lead can review.