RTL design of a RISC-V ALU with timing closure on an open FPGA flow

Openfield Robotics makes brushless motor controllers. Each board has a Lattice iCE40 UP5K FPGA for PWM timing, and the team wants to replace a separate microcontroller with a small RISC-V core inside the FPGA. That saves about USD 1.40 per board on 40,000 boards a year. The core will run at 24 MHz from the board's oscillator, and the FPGA only has 5,280 logic cells, most of which the PWM logic already uses.

The firmware lead has asked you to deliver the arithmetic logic unit first, because it is the block most likely to limit clock speed. The requirements are: - all RV32I integer register and immediate operations: ADD, SUB, SLL, SLT, SLTU, XOR, SRL, SRA, OR, AND, plus the comparisons the branch unit needs (equal, less-than signed and unsigned); - single-cycle, purely combinational, with registered inputs and outputs in the test wrapper; - no more than 1,000 logic cells, so a full core still fits beside the PWM logic; - timing closed at 24 MHz with at least 10% slack across the worst path, reported by the open place-and-route tool.

You will write the specification from the RISC-V unprivileged ISA, write the RTL in Verilog, verify every operation against a Python golden model with cocotb, synthesise it with Yosys, compare at least two shifter architectures for area and speed, place and route with nextpnr for the iCE40 UP5K, and read the timing report. No board is needed: synthesis and timing analysis run entirely on a laptop. If you do have an iCE40 board, an optional on-board test is welcome but is not marked.

Done looks like a repository with RTL, testbench and build scripts, synthesis and timing reports, and a two-page design note telling the firmware lead how big the ALU is, how fast it runs, and what you would change if the core later needs to run faster.