RISC-V Peripheral in Verilog with a Testbench

GitHub repo or evidence pack + live demo / report + README + milestone logbook

Stack: Verilog or SystemVerilog, Icarus or Verilator, GTKWave

• Problem & requirements15

  Loads, constraints, standards and success criteria are written down before the design starts.

• Calculations & analysis30

  Hand calculations or simulation set out step by step with units, assumptions and a check against a second method or code limit.

• Design output20

  Drawings, models, schematics or code that match the calculations and could be handed to the next person.

• Validation & files15

  Test data, simulation files, calculation sheets or photos attached, with what each one shows.

• Report & judgement20

  A clear report that states the result, its limits, cost or risk, and what you would change next.

Pass 60% · Merit 75% · Distinction 90%