Engineers Clinic
AdvancedEngineering trackCE-ELECTR2-P05

Digital logic design

Design Digital logic design in RTL with a self-checking testbench, coverage, synthesis and timing results. You hand in: CAD/sim files + design report PDF + results + demo media.

Core EngineeringElectronics Engineering
10 Guided Steps120h Internship TierSubmit: CAD/sim files + design report PDF + results + demo mediaVerified CertificateAI Rubric Graded
Core Tech Stack:ProteusKiCadArduinoVHDL
Program Overview

Design Digital logic design in RTL with a self-checking testbench, coverage, synthesis and timing results. You hand in: CAD/sim files + design report PDF + results + demo media.

What you submit

CAD/sim files + design report PDF + results + demo media

Stack: Proteus, KiCad, Arduino, VHDL

How it is graded
  • Problem & requirements15

    Loads, constraints, standards and success criteria are written down before the design starts.

  • Calculations & analysis30

    Hand calculations or simulation set out step by step with units, assumptions and a check against a second method or code limit.

  • Design output20

    Drawings, models, schematics or code that match the calculations and could be handed to the next person.

  • Validation & files15

    Test data, simulation files, calculation sheets or photos attached, with what each one shows.

  • Report & judgement20

    A clear report that states the result, its limits, cost or risk, and what you would change next.

Pass 60% · Merit 75% · Distinction 90%

Learning Outcomes
Graded on: Design correctness
simulation results
standards
report
drawings/BOM. Pass 60% · Merit 75% · Distinction 90%.
Target Audience

Engineering Students

Diploma, B.Tech, B.E., BCA, MCA, or M.Tech students seeking practical experience.

Aspiring Developers

Developers who want to build proof-of-work capstone projects for tech resumes.

Job Seekers

Graduates looking for AI-evaluated code review & verified industry credentials.